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ML13145
UHF Wideband Receiver Subsystem (LNA, Mixer, VCO, Prescaler, IF Subsystem, Coiless Detector)
LOW POWER INTEGRATED RECEIVER FOR ISM BAND APPLICATIONS SEMICONDUCTOR TECHNICAL DATA
Legacy Device: Motorola MC13145
The ML13145 is a dual conversion integrated RF receiver intended for ISM band applications. It features a Low Noise Amplifier (LNA), two 50 linear Mixers with linearity control, Voltage Controlled Oscillator (VCO), second LO amplifier, divide by 64/65 dual modulus Prescalar, split IF Amplifier and Limiter, RSSI output, Coilless FM/FSK Demodulator and power down control. Together with the transmit chip (ML13146) and the baseband chip (MC33410 or MC33411A/B), a complete 900 MHz cordless phone system can be implemented. This device may be used in applications up to 1.8 GHz, and operating temperature TA = -20 to +70C.
48
1
LQFP 48 = -9P PLASTIC PACKAGE CASE 932 CROSS REFERENCE/ORDERING INFORMATION
* Low (<1.8 dB @ 900 MHz) Noise Figure LNA with 14 dB Gain PACKAGE MOTOROLA LANSDALE * Externally Programmable Mixer linearity: IIP3 = 10(nom.) to 17 dBm LQFP 48 MC13145FTA ML13145-9P (Mixer1); IIP3 = 10 (nom.) to 17 dBm (Mixer2) * 50 Mixer Input Impedance and Open Collector Output (Mixer 1 and Note: Lansdale lead free (Pb) product, as it Mixer 2); 50 Second LO (LO2) Input Impedance becomes available, will be identified by a part * Low Power 64/65 Dual Modulus Prescalar (ML12054A type) number prefix change from ML to MLE. * Split IF for Improved Filtering and Extended RSSI Range * Internal 330 Terminations for 10.7 MHz Filters * Linear Coilless FM/FSK Demodulator with Externally Programmable Bandwidth, Center Frequency and Audio level *2.7 to 6.5 V Operation, Low Current Drain (<27 mA, Typ @ 3.6 V) with Power Down Mode (<10 A, Typ) *2.4 GHz RF, 1.0 GHz IF1 and 50 MHz IF2 Bandwidth
P R S C O ut
PIN CONNECTIONS AND FUNCTIONAL BLOCK DIAGRAM
D et G ain D et O ut V CC V CC A F T In R SSI A F T O ut VEE 1 48 V EE 47 BWadj LNA /64, 65 Lim 46 Lim Dec2 45 Lim Dec1 44 Lim In 43 V CC 42 V CC 41 IF Out C ontrol IF 40 IF Dec2 39 IF Dec1 38 IF In 37 V EE 25 VCC 26 V EE 27 IF 1+ 28 IF 1- 29 LinA dj2 30 Mxr2In 31 VCC 32 33 V EE LO 2 34 V EE 35 IF 2+ 36 IF 2- This device contains 626 active transistors. IF2 VEE MC Fadj 2
12 V EE 13 LNA In 14 V EE 15 RF V EE 16 LNA Out 17 V EE 18 Mxr1In 19 Lin Adj1 20 Enable 21 oscC 22 LO oscE 23 oscB 24
11
10
9
8
7
6
5
4
3 Demod
ESD Sensitive -- Handle with Care
IF1
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MAXIMUM RATINGS
Rating Power Supply Voltage Junction Temperature Storage Temperature Range Maximum Input Signal Symbol VCC(max) TJ(max) Tstg Pin Value 7.0 150 - 65 to 150 5.0 Unit Vdc C C dBm
NOTES: 1. Meets Human Body Model (HBM) 250 V and Machine Model (MM) 25 V.
RECOMMENDED OPERATING CONDITIONS
Rating Power Supply Voltage (TA = 25C) Input Frequency (LNA In, Mxr1 In) Ambient Temperature Range Input Signal Level (with minor performance degradation) Symbol VCC VEE fin TA Pin Min 2.7 0 100 - 20 - Typ - 0 - - -10 Max 6.5 0 1800 70 - MHz C dBm Unit Vdc
RECEIVER DC ELECTRICAL CHARACTERISTICS (TA = 25C; VCC = 3.6 Vdc; No Input Signal,
unless otherwise noted) Characteristics Total Supply Current (Enable = VCC) Power Down Current (Enable = VEE) Symbol Itotal Itotal Min 24 - Typ 27 10 Max 34 50 Unit mA A
RECEIVER AC ELECTRICAL CHARACTERISTICS (TA = 25C; VCC = 3.6 Vdc; RF In = 1.0 GHz; 1st LO Freq = 1070.7 MHz; 2nd LO Freq = 60 MHz; fmod = 1.0 kHz; fdev = 40 kHz; IF filter bandwidth = 280 kHz, unless otherwise noted. See Figure 1 Test Circuit)
Characteristics SINAD @ -110 dBm LNA Input 12 dB SINAD Sensitivity (Apps Circuit with C-message filter at DetOut) 30 dB SINAD Sensitivity (No IF filter distortion within 40 kHz) SINAD Variation with IF Offset of 40 kHz (No IF filter distortion within 40 kHz) Noise Figure: LNA, 1st Mixer & 2nd Mixer Power Gain: LNA, 1st Mixer & 2nd Mixer RSSI Dynamic Range RSSI Current -10 dBm @ IF Input -20 dBm @ IF Input -30 dBm @ IF Input -40 dBm @ IF Input -50 dBm @ IF Input -60 dBm @ IF Input -70 dBm @ IF Input -80 dBm @ IF Input -90 dBm @ IF Input Input 1.0 dB Compression Point(Measured at IF output) Input 3rd Order Intercept Point (Measured at IF output) Demodulator Output Swing (50 k || 56 pF Load) IF In Det Out Input Pin LNA In LNA In LNA In LNA In LNA In LNA In IF In IF In Measure Pin Det Out Det Out Det Out Det Out IF Out IF Out RSSI RSSI Symbol SINAD SINAD12dB SINAD30dB - NF G - - 35 - - - 15 - - - - Pin1dB IIP3 Vout - - 0.8 40 35 30 25 20 15 10 5.0 1.0 -18 -8.0 1.0 55 - - - 37 - - - 7.0 - - 1.2 dBm dBm Vpp MIn 12 - - - - 15 - Typ 20 -115 -100 5.0 3.5 19 80 Max - - - - 5.0 25 - Unit dB dBm dBm dB dB dB dB A
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ML13145
RECEIVER AC ELECTRICAL CHARACTERISTICS (TA = 25C; VCC = 3.6 Vdc; RF In = 1.0 GHz; 1st LO Freq = 1070.7 MHz; 2nd LO Freq = 60 MHz; fmod = 1.0 kHz; fdev = 40 kHz; IF filter bandwidth = 280 kHz, unless otherwise noted. See Figure 1 Test Circuit)
Characteristics Demodulator Bandwidth (1.0 dB bandwidth) Prescalar Output Level (10 k //8.0 pF load) Prescaler 64 Frequency = 16.72968 MHz Prescaler 65 Frequency = 16.4723 MHz MC Current Input (High) MC Current Input (Low) Input high voltage Input low voltage Input Current PLL Setup Time [Note 1] SNR @ -30 dBm Signal Input (<40 kHz deviation;with C-Message Filter) Total Harmonic Distortion (<40 kHz deviation;with C-Message Filter) Spurious Response SINAD (RF In: -50 dBm) MC Input Pin Measure Pin Det Out PRSCout Symbol BW Vout 0.4 0.4 MC MC Enable Enable Enable PRSCout Iih Iil Vih Vil Iin TPLL 70 -130 VCC - 0.4 0 -50 - - - - 0.51 0.51 100 -100 - - - 10 50 1.0 12 0.6 0.6 130 -70 VCC 0.4 50 - - - - A A V V A nS dB % dB MIn - Typ 100 Max - Unit kHz Vpp
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ML13145
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Figure 1. Test Circuit
MC 10 k 10 n 1.0 n 2.0 k 2.0 k 56 p 10 k 51 k 100 n 68 k 7.2 p
PRSC Out
RSSI 51 k
Det Out 2.7 k
1.0 n LNA In 6.8 n 13 6.8 p 1.5 p 14 15 1.0 n 20 6.8 n 16 17 1.0 M 1.0 p 18 19 1.0 n EN
12
11
10
9
8
7
6
5
4
3 F adj
2
1
100 p
V CC V CC D et O ut P R S C O ut MC D et G ain A F T O ut AFT
48 BWadj 100 k 47 1.0 n 46 Lim 100 n 45 1.0 n 44 10M7 10M7 *C F 2 1.0 n 40 IF 100 n 39 1.0 n 38 *C F 1 IF In IF Out V CC 43 42 41
LNA
64/65
R SSI
ML13145 C ontrol
V CC
20 21 22 4.7 p
1.0 n 3.3 nH 47 p
23 4.7 p 24 V CC 25 26 27 28 29 30 V CC 31 32 33 34 35 36
37
10 n 1.0 M 1.0 n 1.0 k RF LO 50 16 p V CC 1.0 100 n 1.0 n RF LO2 10 1.0 *CF1 & CF2 = 280 kHz, 6.0 dB BW, 10.7 MHz Ceramic Filter **T1 = Toko Part # 600ENAS-A998EK 100 n T2 TC4 12 p T1** 100 n 10 1.0 1.0 n 10 n 10 p
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ML13145
General The ML13145 is a low power dual conversion wideband FM receiver incorporating a split IF. This device is designated for use as the receiver in analog and digital FM systems such as 900 Mhz ISM Band Cordless phones and wideband data links with data rates up to 150kbps. It contains a 1st and 2nd mixer, 1st and 2nd local oscillator, Received Signal Strength Indicator (RSSI), IF amplifier, limiting IF, a unique coilless quadrature detector, and a device enable function. Current Regulation/Enable The ML13145 is designed for battery powered portable applications. Supply current is typically 27 mA at 3.6 Vdc. Temperature compensating, voltage independent current regulators are controlled by the Enable Pin where "high" powers up and "low" powers down the entire circuit. Low Noise Amplifier (LNA) The LNA is a cascoded common emitter amplifier configuration. Under very large RF input signals, the DC base current of the common emitter and cascode transistors can become very significant. To maintain linear operation of the LNA, adequate dc current source is needed to establish the 2Vbe reference at the base of the RF cascoded transistor and to provide the base voltage on the common emitter transistor. A sensing circuit, together with a current mirror guarantees that there is always sufficient DC base current available for the cascode transistor under all power levels. 1st and 2nd Mixer Each mixer is a double-balanced class AB four quadrant multiplier which may be externally biased for high mixer dynamic range. Mixer input third order intercept point of up to17 dBm is achieved with only 7.0 mA of additional supply current. The 1st mixer has a single-ended input at 50 and operates at 1.0 GHz with -3.0 dB of power gain at approximately 100 mVrms LO drive level. The mixers have open collector differential outputs to provide excellent mixer dynamic range and linearity. 1st Local Oscillator The 1st LO has an on-chip transistor which operates with coaxial transmssion line and LC resonant elements up to 1.8 GHz. A VCO output is available for multi-frequency operation under PLL synthesizer control. RSSI The received signal strength indicator (RSSI) output is a current proportional to the log of the received signal amplitude. The RSSI current output (Pin 7) is derived by summing the currents from the IF and limiting amplifier stages. An increase in RSSI dynamic range, particularly at higher input signal levels is achieved. The RSSI circuit is designed to provide typical-
ly 80 dB of dynamic range with temperature compensation. Linearity of the RSSI is optimized by using external ceramic bandpass filters which have an insertion loss of 4.0 dB and 330 source and load impedance. IF Amplifier The first IF amplifier section is composed of three differential stages with the second and third stages contributing to the RSSI. This section has internal DC feedback and external input decoupling for improved symmetry and stability. The total gain of the IF amplifier block is approximately 40 dB up to 40MHz. The fixed internal input impedance is 330 . When using ceramic filters requiring source and load impedances of 330, no external matching is necessary. Overall RSSI linearity is dependent on having total midband attenuation of 10 dB (4.0 dB insertion loss plus 6.0 dB impedance matching loss) for the filter. The output of the IF amplifier is buffered and the impedance is 330 . Limiter The limiter section is similar to the IF amplifier section except that five stages are used with the middle three contributing to the RSSI. The fixed internal input impedance is 330 . The total gain of the limiting amplifier section is approximately 84 dB. This IF limiting amplifier section internally drives the coilless quadrature detector section. Coilless Quadrature Detector The coilless detector is a unique design which eliminates the conventional tunable quadrature coil in FM receiver systems. The frequency detector implements a phase locked loop with a fully integrated on chip relaxation oscillator which is current controlled and externally adjusted, a bandwidth adjust, and an automatic frequency tuning circuit. The loop filter is external to the chip allowing the user to set the loop dynamics. Two outputs are used: one to deliver the audio signal (detector output) and the other to filter and tune the detector (AFT).
Figure 2. 2nd Mixer NF & Gain versus LO Power
25 20 N O IS E F IG U R E ( dB) 15 NF 10 Gain V CC = 3.6 Vdc TA = 25C P RF = -25 dBm Lim Adj Current = 0 -9.0 -4.0 -1.0 6.0 -10 -12 11 -8.0 -2.0 -4.0 -6.0 G A IN LO POWER (dBm)
5.0 0 -14
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PIN FUNCTION DESCRIPTION
Pin 47 Symbol/Type BWadj See Figure 3. Description Description COILLESS DETECTOR Bandwidth Adjust The deviation bandwidth of the detector response is determined by the combination of an on-chip capacitor and an external resistor to ground. Frequency Adjust The free running frequency of the detector oscillator is defined by the combination of an on-chip capacitor and an external resistor, Radj from frequency adjust pin to ground. VEE, Negative Supply These pins are VEE supply for the coilless detector circuit. AFT Out The AFT is low pass filtered with a corner frequency below the audio bandwidth allowing the error to be added to the center frequency adjust signal at Fadj, Pin 2. The low frequency high pass corner is set by the external capacitor, Ct from AFT out (Pin 3) to AFT in (Pin 4) and external resistor, Rt from AFT out to Fadj (Pin 2). AFT In The AFT in is used to set the buffer transfer function. Detector Gain The AFT buffer is used to set the buffer transfer function. Detector Output Set gain and output level of detector with resistor to Det Out Pin.
2
Fadj
1, 48
VEE
3
AFT Out
4
AFT In
5
Det Gain
6
Det Out
Figure 3. Coilless Detector Internal Circuit
i i Phase Detector ICO V CC
Current Amplifier
V CC
IF
4 AFT In V ref2 Ct Fadj BWadj 47 Rb 2I 2 Rt 3 AFT Out Rf
A*i
A*i
5
RI 6 Det Out
V ref1
2Ib
V EE 48, 1
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ML13145
Pin 8
Symbol/Type VEE
11 V CC
Description
Description VEE, Negative Supply Voltage
9
PRSCout
9 PRSC Out 1.0 mA 8 V EE V CC
Prescaler Output The prescaler output provides typically 500 mVpp drive to the fin pin of a PLL synthesizer. Conjugately matching the interface will increase the drive delivered to the PLL input.
10
MC
10 MC
Dual Modulus Control Current Input This requires a current input of typically 200 App.
11, 12
VCC
VCC, Positive Supply VCC pin is taken to the incoming positive battery or regulated dc voltage through a low impedance trace on the PCB. It decoupled to VEE ground at the pin of the IC.
17 LNA out 15, 16 V EE
14
LNA In
LNA In The input is the base of the common emitter transistor. Minimum external matching is required to optimize the input return loss and gain.
V ref2 V ref1 2.0 mA
13, 15, & 16
VEE
3 13 V EE 14 LNA in 11,12 V CC
VEE, Negative Supply VEE pin is taken to an ample dc ground plane through a low impedance path. The path should be kept as short as possible. A minimum two sided PCB is recommended so that ground returns can be easily made through via holes. LNA Out The output is from the collector of the cascode transistor amplifier. The output may be conjugately matched with a shunt L (needed to dc bias the open collector), and series L and C network.
17
LNAout
19
Mxr1In
V CC
20 LinAdj1
1st Mixer Input The mixer input impedance is broadband 50 for applications up to 2.4 GHz. It easily interfaces with a RF ceramic filter.
20
Lin Adj1
19 Mxr1 In 450 A
1st Mixer Linearity Control The mixer linearity control circuit accepts approximately 0 to 300 A control current to set the dynamic range of the mixer. An Input Third Order Intercept Point, IIP3 of 17 dBm may be achieved at 300 A of control current.
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Pin 21
Symbol/Type Enable
Description
Description Enable Enable the receiver by pulling the pin up to VCC.
21 Enable
10 k
26
VEE
VEE, Negative Supply VEE supply for the mixer IF output.
27
27
IF1+
IF1+ 26 V EE
28
IF1-
8 28 IF1-
1st Mixer Outputs The Mixer is a differential open collector output configuration which is designed to use over a wide frequency range. The differential output of the mixer has back to back diodes across them to limit the output voltage swing and to prevent pulling of the VCO. Differential to single-ended circuit configuration and matching options are shown in the Test Circuit. Additional mixer gain can be achieved by matching the outputs for the desired passband Q. On-board VCO Transistor The transistor has the emitter, base, collector, VCC, and VEE pins available. Internal biasing which is compensated for stability over temperature is provided. It is recommended that the base pin is pulled up to VCC through an RFC chosen for the particular oscillator center frequency .
22
Collector
25
23
Emitter
V CC 24
24
Base
Base
18, 26
25
VCC
V EE 23 Emitter 2.0 mA 500 A
VCC, Positive Supply Voltage A VCC pin is provided for the VCO. The operating supply voltage range is from 2.7 Vdc to 6.5 Vdc.
18, 26
VEE
22 Collector
VEE, Negative Supply Voltage
29
Lin Adj2
31, V CC
29 Lin Adj2
2nd Mixer Linearity Control The mixer linearity control circuit accepts approximately 0 to 400 A control current to set the dynamic range of the mixer. An Input Third Order Intercept Point, IIP3 of 17 dBm may be achieved at 400 A of control current. IIP3 default with no external bias is 10 dBm.
30
Mxr2 In
30 Mxr2 In 450 A
2nd Mixer Input The mixer input impedance is broadband 50 .
31
VCC
VCC, Positive Supply
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ML13145
Pin 32, 34
Symbol/Type VEE
V CC
Description
Description VEE, Negative Supply Voltage
LO Out+ (to Mxr2) LO Out-
33
LO2
33 LO2 32 V EE 390 A
2nd Local Oscillator The 2nd LO input impedance is broadband 50 ; it is driven from an external 50 source. Typical level is -15 to -10 dBm.
35
IF2+
35 IF2+ 34 V EE
2nd Mixer Outputs The Mixer is a differential open collector configuration.
36
IF2-
36 IF2-
37 38
VEE IF In
See Figure 4.
VEE, Negative Supply Voltage IF Amplifier Input IF amplifier input source impedance is 330 .. The three stage amplifier has 40 dB of gain with 3.0 dB bandwidth of 40 MHz. IF Decoupling These pins are decoupled to VCC to provide stable operation of the limiting IF amplifier. IF Amplifier Output IF amplifier output load impedance is 330 . VCC, Positive Supply Voltage RSSI The RSSI circuitry in the 2nd & 3rd amplifier stages outputs a current when the output of the previous stage enters limiting. The net result is a RSSI current which represents the logarithm of the IF input voltage. An external resistor to ground is used to provide a voltage output.
39, 40
IF Dec1, IF Dec2 IF Out VCC RSSI
41 42 7
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Figure 4. IF Amplifier Functional Diagram
RSSI 39 IF Dec1
38 IF In 40 IF Dec2 41 IF Out
Pin 43 44
Symbol/Type VCC Lim In See Figure 5.
Description
Description VCC, Positive Supply Voltage Limiting Amplifier Input Limiting amplifier input source impedance is 330 . This amplifier has 84 dB of gain with 3.0 dB bandwidth of 40 MHz; this enables the IF and limiting ampliers chain to hard limit on noise. If Decoupling These pins are decoupled to VCC to provide stable operation of the 2nd IF limiting amplifier. RSSI The RSSI circuitry in the 2nd, 3rd, & 4th amplifier stages outputs a current when the output of the previous stage enters limiting. The net result is a RSSI current which represents the logarithm of the IF input voltage. An external resistor to ground is used to provide a voltage output.
45, 46
Lim Dec1, Lim Dec2 RSSI
7
Figure 5. Limiter Amplifier Functional Diagram
7 RSSI 45 Lim Dec1
44 Lim In 46 Lim Dec2
Lim+ Demod Lim-
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ML13145
Figure 6. 2nd Mixer Gain versus LO Drive
-6.0 -6.4 -6.8 -7.2 -7.6 -8.0 -20 V CC = 3.6 V TA = 25C P RF = -25 dBm Lin Adj Current = 400A P1dB ( dB) 6.0 5.0 4.0 3.0 2.0 1.0 0 -20
Figure 7. 2nd Mixer P1dB versus LO Drive
G A IN ( dB)
V CC = 3.6 V TA = 25C Lin Adj Current = 400A -18 -16 -14 -12 -1 0
-18
-16
-14
-12
-10
LO DRIVE (dBm)
LO DRIVE (dBm)
Figure 8. 2nd Mixer IP3/P1dB versus Lin Adj Current
18 16 14 12 dBm 10 8.0 6.0 4.0 2.0 0 0 100 200 300 400 500 600 LIN ADJ CURRENT ( A) -7.0 0 100 P 1dB -6.8 IP3 G A IN ( dB) V CC = 3.6 V TA = 25C P LO = -15 dBm Adj Channel = 75 kHz -6.4 -6.6 -6.2 -6.0
Figure 9. 2nd Mixer Gain versus Lin Adj Current
V CC = 3.6 V TA = 25C P LO = -15 dBm P RF = -25 dBm
200
300
400
500
60 0
LIN ADJ CURRENT ( A)
Figure 10. Test Circuit for Figures 6 thru 9.
Lin Adj Current
5.1 k 10 n
29 Lin Adj2 V CC 30 Mxr2 In IF2+ 35 T1 IF out
RF in
LO2 in
33 LO2
IF2-
1.0 k 36 16:1 T1 = Toko 600ENAS-A998EK
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LANSDALE Semiconductor, Inc.
Figure 11. Fadj Current versus IF Frequency
500 450 F adj R E S IS TO R ( K ) 400 C U R R ENT ( A ) 350 300 250 200 150 100 5.0 10 IF FREQUENCY (MHz) 15 20 7.0 6.0 5.0 4.0 3.0 2.0 1.0 5.0
Figure 12. Fadj Resistor versus IF Frequency
10 IF FREQUENCY (MHz)
15
20
Figure 13. BWadj Resistor versus BWadj Current
900 800 IF F R E Q U E N C Y ( MH z) 700 C U R R ENT ( A ) 600 500 400 300 200 100 1.0 2.0 3.0 4.0 5.0 6.0 10.90 10.85 10.80 10.75 10.70 10.65 10.60 10.55 1.0 2.0
Figure 14. IF Frequency versus BWadj Current
3.0
4.0
5.0
6. 0
BWadj CURRENT ( A)
BWadj CURRENT ( A)
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ML13145
Table 1. LNA S-Parameters: 3.6 Vdc
Freq (MHz) 25 50 100 150 200 300 400 450 500 750 800 850 900 950 1000 1250 1500 1750 2000 2250 2500 2750 3000 S11 Mag 0.84 0.84 0.83 0.81 0.78 0.73 0.66 0.64 0.62 0.51 0.49 0.47 0.46 0.44 0.45 0.55 0.48 0.43 0.43 0.45 0.47 0.51 0.55 S11 Ang -3.0 -71 -15 -22 -28 -41 -50 -54 -59 -77 -80 -81 -82 --82 -81 -94 -120 -126 -135 -145 -155 -167 -180 S21 Mag 10.8 10.7 10.3 10. 9.6 9.0 7.8 7.4 7.0 5.5 5.2 4.9 4.6 4.3 3.9 3.5 3.1 2.5 2.1 1.8 1.5 1.2 1.0 S21 Ang 176 171 162 154 147 132 116 111 106 80 75 71 67 62 58 47 24 6.9 -9.9 -27 -43 -60 -78 S12 Mag 0.00005 0.0004 0.0006 0.0011 0.001 0.002 0.00070 0.0014 0.0009 0.0013 0.002 0.004 0.0057 0.008 0.014 0.029 0.02 0.0066 0.0099 0.017 0.021 0.03 0.039 S12 Ang -27 76 61 91 60 42 22 39 69 -51 -80 -120 -130 -142 -162 140 63 79 129 133 132 130 120 S22 mag 1.0 1.0 0.99 0.99 0.99 0.99 0.95 0.96 0.96 0.94 0.93 0.92 0.92 0.91 0.95 0.099 0.94 0.93 0.92 0.91 0.89 0.88 0.85 S22 Ang -1.2 -3.7 -4.9 -7.3 -9.7 -15 -19 -21 -23 -33 -36 -37 -38 -40 -41 -50 -65 -74 -85 -96 -106 -118 -129
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ML13145
Figure 15. ML 13145 Evaluation PCB Schematic
L2 5.6 n C 5 100 p R1 C 6 1.0 n U /D
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VC C C 45 3.3 p LN A O ut LN A O ut 17 C 8 0.01 C 2 1.5 p C 3 100 p 19 Mxr1 In IF 1+ 27 VC C C 12 1.0 n C 46 2.0 p IF 1- 28 23 oscE L9 U /D 24 oscB IF 10 C 15 0.01 C 16 0.01 33 LO 2 IF 2- 36 C 33 1.0 n 20 Lin A dj1 IF D ec1 39 29 Lin A dj2 IF D ec2 40 R 9 68 k 47 BWadj 2 F adj Lim D ec1 45 3 A F T O ut C 43 100 p C 41 100 p C 42 100 p C 35 0.01 4 A F T In Lim D ec2 46 Lim In 44 D et G ain 5 Rx EN R 6 51 k 21 E nable D et O ut 6 R SSI 7 R x MC R 12 U /D 10 MC P R S C O ut 9 R 14 51 k C 54 1.0 n C 32 0.01 FRx R 5 27 k C 31 100 p D et O ut R SSI C 29 1.0 n C 28 1.0 n CF3 C 30 0.1 VC C C 23 1.0 n C 24 0.1 C 37 1.0 n C 39 1.0 n R 11 68 k C 38 1.0 n R 10 2.7 k IF In 38 IF O ut 41 C 27 1.0 n C 26 1.0 n C 25 0.1 C 34 1.0 n VC C R 8 U /D C 20 30 p CF2 VC C R 7 U /D 30 Mxr2 In IF 2+ 35 C 19 36 p L5 2.7 L4 2.7 T P 3 IF 2 I/O JP 2 Jumper C 17 100 p C 18 0.01 IF In VC C L8 U /D C 52 U /D C 14 2.0 - 4.0 p L7 2.7 n C 47 2.0 p C 48 100 p D 1 MMBV 809 C 13 100 p R 13 51 22 oscC C 9 16 p C 7 100 p T1 C 11 12 p C 53 0.01 C 10 10 p TP 5 IF 1 O ut IF 1 O ut IF 10 VC C R 2 10 C 1 100 p 14 LN A In L1 6.8 n U1 ML13145 C 21 1.0 n C 22 0.1 TP 4 IF O ut
LN A I n
CF1
480/481
Mxr1 In
C 51 100 p
Rx PD
R 3 33 k
oscB
Mxr2 In
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LO 2
TP 1
VC C
L6 R F C
Figure 15.
C 50 1.0
G nd
C 49 22
C 40 10
C 36 1.0 n
TP 2
C 44 100 p
JP 1
D et O ut R SSI Rx EN
Rx PD
R X MC
1 2 3 4 5 6 7 8 9 10
FRx
LANSDALE Semiconductor, Inc.
H 5X 2
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LANSDALE Semiconductor, Inc.
ML13145
Legacy Applications Information
Figure 16. Evaluation PCB Component Side Figure 17. Evaluation PCB Solder Side
2.25
2.25
2.5
2.5
CF1 CF2,CF3 C1, C3, C5, C7, C13, C17, C31, C41, C42, C43, C44, C48, C51 C2 C6, C12, C21, C23, C26, C27, C28, C29, C33, C34, C36, C37, C38, C39, C54 C8, C15, C16, C18, C32, C53 C9 C10 C11 C14 C19 C20 C22, C24, C25, C30, C35 R2, C40
480/481 10.7M 100 p 1.5 p 1.0 n 0.01 16 p 10 p 12 p 2.0-4.0 p 36 p 39 p 0.1 10
C45 C46, C47 C49 C50 R1, R7, R8, L8, L9, R12, C52 L1 L2 L4, L5 L6 L7 R3 R5 R6,R14 R11,R9 R10 R13 T1 U1
3.3 p 2.0 p 22 1.0 U/D 6.8 n 5.6 n 2.7 RFC 2.7 n 33 k 27 k 51 k 68 k 2.7 k 51 A099 ML13145
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Legacy Applications Information
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ML13145
LANSDALE Semiconductor, Inc.
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. "Typical" parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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